1. Field of the Invention
The current invention generally relates to logic on semiconductor chips. More specifically the current invention is directed to increasing performance margin of logic paths on the chips, consistent with environmental conditions.
2. Description of the Related Art
Semiconductor chips comprising logic circuits arranged in logic paths that perform useful functions are well known. For example, modern computer processors are built with one or more semiconductor chips with logic circuits arranged in such a way as to perform addition, shifting, rotating, comparing and many other functions needed to perform the operation of the computer processor. Storage used by the modern computer processors comprise dynamic random access memory (DRAM) and static random access memory (SRAM) that are also built on semiconductor chips.
Complementary Metal Oxide Semiconductor (CMOS) logic circuitry is the predominant semiconductor technology used in modern electronic systems, including computer systems. Logic paths in a semiconductor chip using CMOS logic circuitry have delays that are dependent on a number of factors. Process variations, such as FET (field effect transistor) channel length are a major contributor to delays of individual logic blocks, such as NANDs and NORs, which contribute to delays of logic paths. For example, a chip processed such that FET channel lengths are at the short end of the process variation will have path delays that are less than path delays on chips of the same design, but processed such that FET channel lengths are at the long end of the process variation. Carrier mobility, interconnection wiring, implant doping, and many other characteristics of the FETs and interconnect all have process variations that affect delay of individual logic blocks, and, ultimately, path delays. The process variations in delay cited above remain substantially constant for the life of a particular semiconductor chip.
External conditions also affect delays of individual logic blocks and path delays. Typically, CMOS circuits become slower, that is, have longer delays, as temperature increases. For example, in an exemplary CMOS technology, delay increases 0.2% for each degree Centigrade that temperature increases. Supply voltage has a major effect on delays. For example, in the exemplary CMOS technology, a 1% increase in the supply voltage causes a 0.6% decrease in delays of the logic circuits. Power and supply voltage on CMOS chips are interrelated; that is, as supply voltage increases, power also increases. Power is dissipated in two ways, called static power and dynamic power. Static power in CMOS circuits is primarily due to leakage currents.
In older, lower performance CMOS processes, static power was very low, and often negligible. FET channel lengths were relatively long, limiting leakage from FET drains to the corresponding FET sources. FET threshold voltages were high enough to make subthreshold currents negligible in most applications. FET gate oxide thicknesses were relatively thick, limiting leakage from the FET gate to the FET body, the FET source, and the FET drain to extremely small values.
In modern, high-performance CMOS processes, channel lengths have become very small, allowing some drain to source leakage. FET threshold voltages have been reduced to the point where subthreshold currents are no longer negligible in many applications. Gate oxide thicknesses have become only a few atomic layers thick; leakage through such a thin FET gate oxide to underlying regions results in a significant fraction of a total power dissipated by the chip. Dynamic power is dissipated as capacitances are charged and discharged during normal operation of the chip, as well as “shoot-through” current that occurs during a transition from a low to a high or a high to a low, when both a PFET (P-channel FET) and an NFET (N-channel FET) are partially conducting. Path delays therefore can be reduced by raising the supply voltage; however, raising supply voltage raises temperature on the chip.
A method and apparatus is needed to improve performance margin by dynamically adjusting the voltage supply to be as high as possible within a voltage range without causing the semiconductor chip to operate at an unacceptable temperature.